MIPS Leverages Siemens Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISCV

Release date May. 30, 2023, 03:10 am EDT
San Jose, CA, United States
MIPS Leverages Siemens Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISCV
ProFPGA platform for rapid prototyping of P8700 core based SoCs

MIPS, a leading developer of highly scalable RISC processor IP, has collaborated with Siemens Digital Industries Software, a global electronic design automation leader, to speed time-to-market and accelerate software development for customers of the new MIPS eVocore P8700 RISC-V multiprocessor.

Under the collaboration, MIPS will use Siemens' Veloceā„¢ proFPGA platform to demonstrate MIPS' high-performance intellectual property (IP) cores, including MIPS' eVocore P8700, which recently took top honors at Embedded World. The P8700, one of the industry's highest performance, most scalable RISC-V multiprocessor IP, has already been adopted for applications including autonomous driving and advanced driver assistance systems (ADAS).

MIPS CPUs on Siemens' Veloce proFPGA platform can enable customers to validate their end systems before silicon. Customers can add their custom logic and accelerators and validate their system-on chip (SoC) for optimal functionality. In addition, Siemens' Veloce proFPGA platform will give customer software teams full access to the platform's prototyping hardware system, software tools, and debug trace hooks, enabling early software development and hardware-software codesign.

"As a growing number of SoC designers are moving to RISC-V for their future designs, we are seeing increasing interest in our eVocore processors because of the unrivaled level of scalability they provide," said MIPS CEO Desi Banatao. "We are delighted to collaborate with Siemens to enable our customers to benefit from all the features and tools of our best-in-class eVocore P8700 together with the scalable capacity and flexibility offered by Siemens' Veloce proFPGA platform."

The P8700 brings a new level of performance to RISC-V as the first Out-of-Order (OoO) processor with coherent multi-threaded, multi-core and multi-cluster scalability. MIPS customers can also add their own accelerators to systems with the P8700 while maintaining coherency. With the ability to support up to 64 clusters and 8 cores per cluster and 2 threads per core, P8700 provides a highly scalable CPU solution, and Veloce proFPGA is an ideal platform to help them get started on development.

Siemens' Veloce proFPGA platform can dramatically lower the adoption barrier of the FPGA desktop prototype solution. Together with the performance that is possible to reach thanks to its architecture innovations, the solution is easy to deploy, and engineers can now bring up on their own lab environment quickly and reliably.

The flexibility of the Veloce proFPGA platform allows the user the possibility to use the desktop prototype within various types of workloads, with onboard testbenches and in-circuit connections to external hardware as Ethernet generators or PCI Express buses. This platform enables MIPS to support multiple configurations, starting with a single core, single threaded CPU up to multi-core, multi-cluster configurations. The scalable and flexible SoC platform from Siemens can help reduce development time for customer prototypes and can enable very quick proof-of-concept of their end system with MIPS CPUs.

"The increasing complexity of SoC designs requires more substantial prototyping tools," said Jean-Marie Brunet, vice president and general manager of HW-assisted verification at Siemens Digital Industries Software. "We are pleased to help MIPS customers and developers keep up with the accelerating pace of innovation by providing powerful and scalable prototyping solutions tailored to their use cases, from IP to sub-system to SoC."


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